//Greg Chabala
//ECE483 lab 3
//ALU one bit slice

`timescale 1ns/100ps

module alu_slice(Y, cout, rightout, leftout, A, B, s, cin, rightin, leftin);
    output Y;
    output cout;
    output rightout, leftout;
    input A;
    input B;
    input [3:0] s;
    input cin;
    input rightin, leftin;

    wire sum;
    wire Bin, Lout;

    mux_4to1 arith(Bin, s[1:0], B, ~B, 1'b0, 1'b1);
    mux_4to1 logic(Lout, s[1:0], A&B, A|B, A^B, ~A);
    adder_1bit madd(sum, cout, A, Bin, cin);
    mux_4to1 everything(Y, s[3:2], sum, Lout, rightin, leftin);

    assign rightout = A;
    assign leftout = A;

endmodule