//Greg Chabala
//ECE483 lab 3
//ALU one bit slice testbench

`timescale 1ns/100ps

module alu_slice_tb;
    wire Y;
    wire cout;
    wire rightout, leftout;
    reg A;
    reg B;
    reg [3:0] s;
    reg cin;
    reg rightin, leftin;

    integer fid;

alu_slice my_home_slice(Y, cout, rightout, leftout, A, B, s, cin, rightin, leftin);

initial begin

      fid = $fopen("./alu_slice.out");
      $fmonitor(fid, $time, " Y = %b, cout = %b, rightout = %b, leftout = %b, A = %b, B = %b, s = %h, cin = %b, rightin = %b, leftin = %b", Y, cout, rightout, leftout, A, B, s, cin, rightin, leftin);
      $dumpfile("./alu_slice.dmp");
      $dumpvars(2, alu_slice_tb);

      #1 A = 0; B = 0; s = 4'b0; cin = 0; rightin = 0; leftin = 0;

   end

   initial begin
      #6400 $finish;
   end

   always begin
      #10 leftin = ~leftin;
   end

   always begin
      #20 rightin = ~rightin;
   end

   always begin
      #40 cin = ~cin;
   end

   always begin
      #80 B = ~B;
   end

   always begin
      #160 A = ~A;
   end

   always begin
      #320 s = s + 1;
   end
endmodule