//Greg Chabala
//control unit testbench

`timescale 1ns/100ps

module control_unit_tb;

	reg		clk;			// Common clock
	reg		reset;
	wire	[5:0]   load_ctl;
	wire	[5:0]	clr_ctl;		//0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR
	wire	[5:0]	inc_ctl;
	wire		flag_en;
        wire	[2:0]   bus_ctl;
	wire		cin;
	wire		ALU_sel;
	wire	[3:0]	op_sel;
	wire	read_mem, write_mem;

	reg	[15:0]	IR_out;	        	// input from the IR
	reg	[3:0]	flag_out;		// input from the status register

	integer		fid;			// File ID to dump the monitor 


	control_unit CTL(load_ctl, inc_ctl, clr_ctl, cin, flag_en, ALU_sel, op_sel, read_mem, write_mem, bus_ctl, IR_out, flag_out, clk, 1'b1, reset);


	initial begin
		clk = 1'b0;
		forever #10 clk <= ~clk;
	end

	initial begin                      //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR

		fid = $fopen("./control_unit.out");

		$fmonitor(fid, $time, " clk=%b, IR_out=%h, flag_out=%b, load_ctl=%b, clr_ctl=%b, inc_ctl=%b, flag_en=%b, bus_ctl=%b, cin=%b, ALU_sel=%b, op_sel=%b, read_mem=%b, write_mem=%b, reset=%b", 
			clk, IR_out, flag_out, load_ctl, clr_ctl, inc_ctl, flag_en, bus_ctl, cin, ALU_sel, op_sel, read_mem, write_mem, reset);

		$dumpfile("./control_unit.dmp");
		$dumpvars(4, control_unit_tb);

		#10 	IR_out <= 16'h0000;
			flag_out <= 4'b0000;
			reset <= 1'b1;

		#20	reset <= 1'b0;

		#20 	//CLA
			IR_out <= 16'h7800;

		#20	//LDA
			IR_out <= 16'h2000;

		#20     //LDA still
			IR_out <= 16'h2000;

		#20	//ADD
			IR_out <= 16'h1000;

		#20	//ADD still
			IR_out <= 16'h1000;

		#20	//AND
			IR_out <= 16'h0000;

		#20	//AND still
			IR_out <= 16'h0000;

		#20	//CIR
			IR_out <= 16'h7080;

		#20	//CIL
			IR_out <= 16'h7040;


		#40 $finish;
	end


endmodule