/* Greg Chabala
This file describes a four bit counter with
parallel load and synchronus load and clear 
inputs and a count enable input */

`timescale 1ns/100ps

module counter_4bit (out, in, load, clear, cnt, clk);
        input   [3:0]   in;     /* parallel load input */
	input           load;   /* load parallel input */
	input           clear;  /* clear the counter to 4'h0 */
	input           cnt;    /* count enable input */
	input           clk;    /* clock input */
	output  [3:0]   out;    /* output of counter */

	reg     [3:0]   Q;      /* four bit register to hold count */

	/* State changes only on positive clock transitions */
	always @(posedge clk)
	begin
		if(clear == 1'b1) /* If clear is high, it has priority */
			Q <= 4'b000;
		else if(load == 1'b1) /* load has the next highest */
			Q <= in;
		else if(cnt == 1'b1) /* followed by count enable */
			Q <= Q + 4'b0001;
		else
			Q <= Q;
	end

	/* Set the output to always be equal to the internal state */
	assign out = Q;

endmodule