`timescale 1ns/100ps

module counter_4bit_tb;

        reg     [3:0]   pin;    /* parallel load input */
        reg             load;
        reg             clear;
        reg             cnt;
        reg             clk;

        wire    [3:0]   reg_out; /* output of counter */
        integer         fid;    /* file handle for output file */

        /* invoke an instance of a counter_4bit within the test bench */
        counter_4bit    counter(reg_out, pin, load, clear, cnt, clk);

        /* first we need to setup the clock signal */
        initial begin
                clk = 1'b0;
                forever #10 clk <= ~clk; /* clk has a 20ns period */
        end

        /* now we need to stimulate the module */
        initial begin
                /* Setup the loging facilities */

                /* open a file handle for the output file */
                fid = $fopen("./counter_4bit.out");

                /* anytime load, clear, cnt or reg_out change log these changes to file */
                $fmonitor(fid, $time, " load = %b, clear = %b, cnt = %b, reg_out = %b",
                        load, clear, cnt, reg_out ) ;

                /* Set the waveform dump file */
                $dumpfile("./counter_4bit.dmp");

                /* Dump all signals two levels deep,
                        with respect to counter_4bit_tb module */
                $dumpvars(2, counter_4bit_tb);

                /* Start stimulating the module */
                clear <= 1'b1;
                load <= 1'b0;
                cnt <= 1'b0;
                pin <= 4'b0110;
                #20 clear <= 1'b0;
                #20 load <= 1'b1;
                #20 load <= 1'b0;
                cnt <= 1'b1;
                #100 cnt <= 1'b0;
                clear <= 1'b1;
                #20 clear <= 1'b0;
                #20 $finish;
        end

endmodule