//Greg Chabala
//SEP Data Unit

module data_unit(IR_out, flag_out, mem_bus, ram_rd_nwr, clk, load_line, clr_line, inc_line, read, write, ALU_sel, op_sel, flag_en, cin, bus_sel, address_out, DR_zero, AC_lh);

output [3:0] flag_out;
output [15:0] IR_out;
input [15:0] mem_bus;
output ram_rd_nwr;
input clk;
input read, write;

wire [15:0] MEM_out;
wire [15:0] bus;            //no one likes to ride the bus -Socrates
wire [11:0] AR_out;
wire [11:0] PC_out;
wire [15:0] DR_out;
wire [15:0] DPU_out;
wire [15:0] TR_out;
input [5:0] load_line;      //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR
input [5:0] clr_line;       //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR
input [5:0] inc_line;       //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR
output [11:0] address_out;
output DR_zero;
output [1:0] AC_lh;

//extra lines
input cin;
input flag_en;
input ALU_sel;
input [3:0] op_sel;
input [2:0] bus_sel;

reg_12bit AR(AR_out, bus[11:0], load_line[0], clr_line[0], clk, inc_line[0]);
reg_12bit_pc PC(PC_out, bus[11:0], load_line[1], clr_line[1], clk, inc_line[1]);
reg_16bit DR(DR_out, bus, load_line[2], clr_line[2], clk, inc_line[2]);
reg_16bit IR(IR_out, bus, load_line[4], clr_line[4], clk, inc_line[4]);
reg_16bit TR(TR_out, bus, load_line[5], clr_line[5], clk, inc_line[5]);
sep_dpu DPU(DPU_out, flag_out, DR_out, op_sel, cin, clk, flag_en, load_line[3], clr_line[3], inc_line[3], ALU_sel);
mux_8to1_16bit THE_BUS(bus, bus_sel, 16'b0, AR_out, PC_out, DR_out, DPU_out, IR_out, TR_out, MEM_out);

assign DR_zero = ~&DR_out;

assign AC_lh[0] = DPU_out[0];
assign AC_lh[1] = DPU_out[15];

memory_unit MEM(MEM_out, address_out, mem_bus, bus, AR_out, read, write, ram_rd_nwr);

endmodule


//DPU unit

module sep_dpu(dpu_out, flag_out, data_in, sel, cin, clk, flag_en, ac_en, acclr, AC_inc, ALU_sel);
           output  [15:0] dpu_out;               // DPU output
           output  [3:0]  flag_out;              // flag outputs
           input   [15:0] data_in;               // data input
           input   [3:0]  sel;                   // operation selection
           input          cin;                   // carry in
           input          clk;                   // clock input
           input          flag_en;               // flag enable
           input          ac_en;                 // ac enable
           input          acclr;                 // ac clear
           input          AC_inc;                // AC increment
           input          ALU_sel;		 // selects ALU inputs

      wire [15:0] Y;
      wire [15:0] ALU_A;
      wire [15:0] ALU_B;
      wire cout15;
      wire rightout, leftout;
      wire [3:0] flag_lines;

mux_2to1_16bit A_in(ALU_A, ALU_sel, data_in, dpu_out);
mux_2to1_16bit B_in(ALU_B, ALU_sel, dpu_out, data_in);
      

//flags 0:  overflow
//      1:  carry
//      2:  sign
//      3:  zero


sep_alu my_alu(Y, flag_lines[1], cout15, rightout, leftout, ALU_A, ALU_B, sel, cin, flag_out[1], flag_out[1]);
reg_16bit AC(dpu_out, Y, ac_en, acclr, clk, AC_inc);
reg_4bit FLAG(flag_out, flag_lines, flag_en, 1'b0, clk, 1'b0);
assign flag_lines[0] = flag_lines[1] ^ cout15;
assign flag_lines[2] = dpu_out[15];
assign flag_lines[3] = ~&dpu_out;

endmodule