// Generated by ac_shell v4.0-s008 on Thu Oct 06 17:47:56 CST 2005.

// Restrictions concerning the use of Ambit BuildGates are covered in the
// license agreement.  Distribution to third party EDA vendors is
// strictly prohibited.

module data_unit(IR_out, flag_out, mem_bus, ram_rd_nwr, clk, load_line, clr_line
		, inc_line, read, write, ALU_sel, op_sel, flag_en, cin, bus_sel
		);

	output [15:0] IR_out;
	output [3:0] flag_out;
	input [15:0] mem_bus;
	output ram_rd_nwr;
	input clk;
	input [5:0] load_line;
	input [5:0] clr_line;
	input [5:0] inc_line;
	input read;
	input write;
	input ALU_sel;
	input [3:0] op_sel;
	input flag_en;
	input cin;
	input [2:0] bus_sel;

	wire [15:0] TR_out;
	wire [15:0] DPU_out;
	wire [15:0] DR_out;
	wire [11:0] PC_out;
	wire [11:0] AR_out;
	wire [15:0] bus;
	wire [15:0] MEM_out;



	buf_1 i_2840(.ip(bus[0]), .op(n_2837));
	buf_1 i_314(.ip(bus[2]), .op(n_325));
	buf_1 i_199(.ip(bus[1]), .op(n_209));
	buf_1 i_1041(.ip(bus[6]), .op(n_1019));
	buf_1 i_275(.ip(bus[12]), .op(n_235));
	buf_1 i_227(.ip(bus[14]), .op(n_188));
	buf_1 i_185(.ip(bus[10]), .op(n_141));
	buf_1 i_71(.ip(bus[15]), .op(n_91));
	buf_1 i_405(.ip(bus[11]), .op(n_327));
	buf_1 i_361(.ip(bus[7]), .op(n_279));
	buf_1 i_317(.ip(bus[13]), .op(n_233));
	buf_1 i_274(.ip(bus[8]), .op(n_185));
	buf_1 i_221(.ip(bus[5]), .op(n_138));
	buf_1 i_105(.ip(bus[9]), .op(n_90));
	buf_1 i_3009(.ip(bus[3]), .op(n_4651));
	reg_16bit_2 DR(.out(DR_out), .in({n_91, n_188, n_233, n_235, n_327, 
		n_141, n_90, n_185, n_279, n_1019, n_138, bus[4], n_4651, n_325,
		 n_209, n_2837}), .load(load_line[2]), .clear(clr_line[2]), .clk
		(clk), .inc(inc_line[2]));
	reg_16bit_1 IR(.out(IR_out), .in({n_91, n_188, n_233, n_235, n_327, 
		n_141, n_90, n_185, n_279, n_1019, n_138, bus[4], n_4651, n_325,
		 n_209, n_2837}), .load(load_line[4]), .clear(clr_line[4]), .clk
		(clk), .inc(inc_line[4]));
	reg_16bit_0 TR(.out(TR_out), .in({n_91, n_188, n_233, n_235, n_327, 
		n_141, n_90, n_185, n_279, n_1019, n_138, bus[4], n_4651, n_325,
		 n_209, n_2837}), .load(load_line[5]), .clear(clr_line[5]), .clk
		(clk), .inc(inc_line[5]));
	memory_unit MEM(.out(MEM_out), .mem_bus(mem_bus), .in({n_91, n_188, 
		n_233, n_235, n_327, n_141, n_90, n_185, n_279, n_1019, n_138, 
		bus[4], n_4651, n_325, n_209, n_2837}), .ar_in(AR_out), .read(
		read), .write(write), .ram_rd_nwr(ram_rd_nwr));
	mux_8to1_16bit THE_BUS(.out(bus), .sel(bus_sel), .in1({UNCONNECTED_000, 
		UNCONNECTED_001, UNCONNECTED_002, UNCONNECTED_003, AR_out[11], 
		AR_out[10], AR_out[9], AR_out[8], AR_out[7], AR_out[6], AR_out[5
		], AR_out[4], AR_out[3], AR_out[2], AR_out[1], AR_out[0]}), .in2
		({UNCONNECTED_004, UNCONNECTED_005, UNCONNECTED_006, 
		UNCONNECTED_007, PC_out[11], PC_out[10], PC_out[9], PC_out[8], 
		PC_out[7], PC_out[6], PC_out[5], PC_out[4], PC_out[3], PC_out[2]
		, PC_out[1], PC_out[0]}), .in3(DR_out), .in4(DPU_out), .in5(
		IR_out), .in6(TR_out), .in7(MEM_out));
	sep_dpu DPU(.dpu_out(DPU_out), .flag_out(flag_out), .data_in(bus), .sel(
		op_sel), .cin(cin), .clk(clk), .flag_en(flag_en), .ac_en(
		load_line[3]), .acclr(clr_line[3]), .AC_inc(inc_line[3]), .
		ALU_sel(ALU_sel));
	reg_12bit_pc PC(.out(PC_out), .in({n_327, n_141, n_90, n_185, n_279, 
		n_1019, n_138, bus[4], n_4651, n_325, n_209, n_2837}), .load(
		load_line[1]), .clear(clr_line[1]), .clk(clk), .inc(inc_line[1])
		);
	reg_12bit AR(.out(AR_out), .in({n_327, n_141, n_90, n_185, n_279, n_1019
		, n_138, bus[4], n_4651, n_325, n_209, n_2837}), .load(load_line
		[0]), .clear(clr_line[0]), .clk(clk), .inc(inc_line[0]));
endmodule