//Greg Chabala
//data_unit testbench

`timescale 1ns/100ps

module data_unit_tb;

	wire	[15:0]	mem_bus;
	reg	[15:0]	mem_reg;
        reg      	read, write;
	wire		ram_rd_nwr;
	reg	[3:0]	op_sel;			// ALU control signals
        reg		ALU_sel;		// ALU input switch
	reg		cin;			// Carry In
	reg		clk;			// Common clock
	reg	[5:0]   load_line;
	reg	[5:0]	clr_line;		//0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR
	reg	[5:0]	inc_line;
	reg		flag_en;
        reg	[2:0]   bus_sel;

	wire	[15:0]	IR_out;	        	// Output from the IR
	wire	[3:0]	flag_out;		// Output from the status register
	wire	[11:0]	address;

	integer		fid;			// File ID to dump the monitor 

	assign mem_bus = (ram_rd_nwr == 1)? mem_reg: 16'bzzzzzzzzzzzzzzzz;

	data_unit	u0(IR_out, flag_out, mem_bus, ram_rd_nwr, clk, load_line, clr_line,
                           inc_line, read, write, ALU_sel, op_sel, flag_en, cin, bus_sel, address);

//flags 0:  overflow
//      1:  carry
//      2:  sign
//      3:  zero


	initial begin
		clk = 1'b0;
		forever #10 clk <= ~clk;
	end

	initial begin                      //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR

		fid = $fopen("./data_unit.out");

		$fmonitor(fid, $time, " mem_bus=%h, mem_reg=%h, op_sel=%b, cin=%b, IR_out=%h, flag_out=%b, ram_rd_nwr=%b, read=%b, write=%b, ALU_sel=%b, load_line=%b, clr_line=%b, inc_line=%b, flag_en=%b, clk=%b, bus_sel=%b, address=%h", 
			mem_bus, mem_reg, op_sel, cin, IR_out, flag_out, ram_rd_nwr, read, write, ALU_sel, load_line, clr_line, inc_line, flag_en, clk, bus_sel, address);

		$dumpfile("./data_unit.dmp");
		$dumpvars(4, data_unit_tb);

		#20 	mem_reg <= 16'h0000;
			bus_sel <= 3'b0;
			read <= 1'b1;
			write <= 1'b0;
			op_sel <= 4'b0000;
     			ALU_sel	<= 1'b0;		// ALU input switch
			cin <= 1'b0;			// Carry In
			load_line <= 6'b000000;
			clr_line <= 6'b000000;		//0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR
			inc_line <= 6'b000000;
			flag_en <= 1'b1;

		#20 	//CLA
			clr_line <= 6'b001000;		//0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR

		#20	//LDA
			clr_line <= 6'b000000;
			mem_reg <= 16'h0F04;
			bus_sel <= 3'b111;
			load_line <= 6'b000100;

		#20     //LDA still
			op_sel <= 4'b0010;
			bus_sel <= 3'b011;
			load_line <= 6'b001000;

		#20	//ADD
			mem_reg <= 16'h001F;
			bus_sel <= 3'b111;
			load_line <= 6'b000100;

		#20	//ADD still
			op_sel <= 4'b0000;
			bus_sel <= 3'b011;
			load_line <= 6'b001000;

		#20	//AND
			mem_reg <= 16'h00FF;
			bus_sel <= 3'b111;
			load_line <= 6'b000100;

		#20	//AND still
			op_sel <= 4'b0100;
			bus_sel <= 3'b011;
			load_line <= 6'b001000;

		#20	//CIR
			ALU_sel <= 1'b1;
			op_sel <= 4'b1000;

		#20	//CIL
			op_sel <= 4'hC;


		#40 $finish;
	end

endmodule