//Greg Chabala
//ECE 483 lab 2
//majority function testbench

`timescale 1ns/100ps

module maj_tb;

   reg      m_a;
   reg      m_b;
   reg      m_c;
   wire     m_out;
   integer  fid;

   maj m(m_out, m_a, m_b, m_c);

   initial begin

      fid = $fopen("./maj.out");
      $fmonitor(fid, $time, " out = %b, a = %b, b = %b, c = %b", m_out, m_a, m_b, m_c);
      $dumpfile("./maj.dmp");
      $dumpvars(2, maj_tb);

      #1 m_a = 0; m_b = 0; m_c = 0;

   end

   initial begin
      #100 $finish;
   end

   always begin
      #10 m_a = ~m_a;
   end

   always begin
      #20 m_b = ~m_b;
   end

   always begin
      #40 m_c = ~m_c;
   end

endmodule