`timescale 1ns/100ps

module memory_unit(out, address_out, mem_bus, in, ar_in, read, write, ram_rd_nwr);
        input   [15:0]  in;
        input   [11:0]  ar_in;
        input           read;
        input           write;
        output  [15:0]  out;
        output  [11:0]  address_out;
        output          ram_rd_nwr;
        inout   [15:0]  mem_bus;

        reg     [11:0]  int_address;
        reg     [15:0]  int_data;
        wire            state;          // 0 for read 1 for write

        assign mem_bus = (state == 1'b1)? in : 16'bzzzzzzzzzzzzzzzz;

        assign state = write & ~read;

        assign address_out = ar_in;

        assign ram_rd_nwr = read | ~write;

        assign out = mem_bus;

endmodule