//Greg Chabala

`timescale 1ns/100ps

module mux_4to1(out, sel, in0, in1, in2, in3);

	input	[1:0]	sel; /* mux select line */
	input		in0; /* input 0         */
	input		in1; /* input 1         */
	input		in2; /* input 2         */
	input		in3; /* input 3         */
	output		out; /* output of mux   */

	reg		out; /* this should optimize out */

	always @( sel or in0 or in1 or in2 or in3)

		case (sel)
		    2'b00 :	out <= in0;
		    2'b01 :	out <= in1;
		    2'b10 :	out <= in2;
		    2'b11 :	out <= in3;
		    default :	out <= in0;
		endcase

endmodule