/* mux_8to1_16bit describes an eight to one multiplexer that
   is sixteen bits wide.  It should synthesize as purly combinational
   logic.  The single register should optimize out.                   */

`timescale 1ns/100ps

module mux_8to1_16bit(out, sel, in0, in1, in2, in3, in4, in5, in6, in7);

	input	[2:0]	sel; /* mux select line */
	input	[15:0]	in0; /* input 0         */
	input	[15:0]	in1; /* input 1         */
	input	[15:0]	in2; /* input 2         */
	input	[15:0]	in3; /* input 3         */
	input	[15:0]	in4; /* input 4         */
	input	[15:0]	in5; /* input 5         */
	input	[15:0]	in6; /* input 6         */
	input	[15:0]	in7; /* input 7         */
	output	[15:0]	out; /* output of mux   */

	reg	[15:0]	out; /* this should optimize out */

	/* if any of the inputs to the mux change we want
	   to reevaluate the case statement              */
	always @( sel or in0 or in1 or in2 or in3 
		      or in4 or in5 or in6 or in7)

		case (sel)
		    3'b000 :	out <= in0;
		    3'b001 :	out <= in1;
		    3'b010 :	out <= in2;
		    3'b011 :	out <= in3;
		    3'b100 :	out <= in4;
		    3'b101 :	out <= in5;
		    3'b110 :	out <= in6;
		    3'b111 :	out <= in7;
			/* having a default case ensures
			   that the mux will synthesize 
			   as purely combinational logic */
		    default :	out <= in0;
		endcase

endmodule