`timescale 1ns/100ps

        module mux_8to1_16bit_tb;

                reg     [2:0]   mux_sel;
                reg     [15:0]  mux_in0;
                reg     [15:0]  mux_in1;
                reg     [15:0]  mux_in2;
                reg     [15:0]  mux_in3;
                reg     [15:0]  mux_in4;
                reg     [15:0]  mux_in5;
                reg     [15:0]  mux_in6;
                reg     [15:0]  mux_in7;

                wire    [15:0]  mux_out;
                integer         fid;

                mux_8to1_16bit  mux(mux_out, mux_sel, mux_in0, mux_in1, mux_in2,
                                    mux_in3, mux_in4, mux_in5, mux_in6, mux_in7);

                initial begin

                    fid = $fopen("./mux_8to1_16bit.out");
                    $fmonitor(fid, $time, " out = %h, sel = %b",
                              mux_out, mux_sel ) ;

                    $dumpfile("./mux_8to1_16bit.dmp");
                    $dumpvars(2, mux_8to1_16bit_tb);

                    mux_in0 <= 16'h000;
                    mux_in1 <= 16'h0001;
                    mux_in2 <= 16'h0002;
                    mux_in3 <= 16'h0003;
                    mux_in4 <= 16'h0004;
                    mux_in5 <= 16'h0005;
                    mux_in6 <= 16'h0006;
                    mux_in7 <= 16'h0007;
                    mux_sel <= 3'b000;

                    #20 mux_sel <= 3'b001;
                    #20 mux_sel <= 3'b010;
                    #20 mux_sel <= 3'b011;
                    #20 mux_sel <= 3'b100;
                    #20 mux_sel <= 3'b101;
                    #20 mux_sel <= 3'b110;
                    #20 mux_sel <= 3'b111;
                    #20 mux_sel <= 3'b000;

                    #20 $finish;
                end
        endmodule