/* Greg Chabala */ `timescale 1ns/100ps module reg_12bit_pc (out, in, load, clear, clk, inc); parameter size=12, rVal=2; input [(size-1):0] in; input load, clear, clk, inc; output [(size-1):0] out; reg [(size-1):0] out; always @(posedge clk) if (clear) out <= rVal; else if (load) out <= in; else if (inc) out <= out + 12'b1; else out <= out; endmodule