/* Greg Chabala */

`timescale 1ns/100ps

module reg_16bit (out, in, load, clear, clk, inc);
   parameter size=16, rVal=0;
   input [(size-1):0]  in;
   input load, clear, clk, inc;
   output [(size-1):0] out;
   reg [(size-1):0]    out;

   always @(posedge clk)
      if (clear)
         out <= rVal;
      else if (load)
         out <= in;
      else if (inc)
         out <= out + 16'b1;
      else
         out <= out;

endmodule

module reg_16bit_A (out, clear, clk, inc, shl);
   parameter size=16, rVal=0;
   input clear, clk, inc, shl;
   output [(size-1):0] out;
   reg [(size-1):0]    out;

   always @(posedge clk)
      if (clear)
         out <= rVal;
      else if (shl)
	 out <= out << 1;
      else if (inc)
         out <= out + 16'b1;
      else
         out <= out;

endmodule