`timescale 1ns/100ps

module reg_16bit_tb;

	reg	[15:0]	reg_input;
	reg		reg_load;
	reg		reg_clear;
	reg		clk;
        reg             inc;

	wire	[15:0]	reg_out;
	integer		fid;

	reg_16bit	register(reg_out, reg_input, reg_load, reg_clear, clk, inc);

	initial begin
		clk = 1'b0;
		forever #10 clk <= ~clk;
	end

	initial begin
		
		fid = $fopen("./reg_16bit.out");
		$fmonitor(fid, $time, " out = %h, in = %h, load = %b, clear = %b, inc = %b",
			reg_out, reg_input, reg_load, reg_clear, inc ) ;

		$dumpfile("./reg_16bit.dmp");
		$dumpvars(2, reg_16bit_tb);

		reg_clear <= 1'b1;
		reg_load <= 1'b0;
                inc <= 1'b0;
		reg_input <= 16'hdead;
		#20 reg_clear <= 1'b0;
		#20 reg_load <= 1'b1;
		#20 reg_load <= 1'b0;
		#20 reg_input <= 16'hbeef;
		#20 reg_load <= 1'b1;
		#20 reg_load <= 1'b0;
                #20 inc <= 1'b1;
		#40 inc <= 1'b0;
                reg_input <= 16'h0000;
		reg_clear <= 1'b1;
		#20 reg_clear <= 1'b0;
		#20 $finish;
	end

endmodule