/* Greg Chabala */

`timescale 1ns/100ps

module reg_32bit (out, in, in16, load, ldhi, ldlo, clear, clk, inc, shl, dshl, in0, in1);
   parameter size=32, rVal=0;
   input [(size-1):0]  in;
   input [15:0] in16;
   input load, ldhi, ldlo, clear, clk, inc, shl, dshl, in0, in1;
   output [(size-1):0] out;
   reg [(size-1):0]    out;

   always @(posedge clk)
      if (clear)
         out <= rVal;
      else if (load)
         out <= in;
      else if (ldhi)
	 begin
		out[31] <= in16[15];
		out[30] <= in16[14];
		out[29] <= in16[13];
		out[28] <= in16[12];
		out[27] <= in16[11];
		out[26] <= in16[10];
		out[25] <= in16[9];
		out[24] <= in16[8];
		out[23] <= in16[7];
		out[22] <= in16[6];
		out[21] <= in16[5];
		out[20] <= in16[4];
		out[19] <= in16[3];
		out[18] <= in16[2];
		out[17] <= in16[1];
		out[16] <= in16[0];
	 end
      else if (ldlo)
	 begin
		out[15] <= in16[15];
		out[14] <= in16[14];
		out[13] <= in16[13];
		out[12] <= in16[12];
		out[11] <= in16[11];
		out[10] <= in16[10];
		out[9] <= in16[9];
		out[8] <= in16[8];
		out[7] <= in16[7];
		out[6] <= in16[6];
		out[5] <= in16[5];
		out[4] <= in16[4];
		out[3] <= in16[3];
		out[2] <= in16[2];
		out[1] <= in16[1];
		out[0] <= in16[0];
	 end
      else if (inc)
         out <= out + 16'b1;
      else if (shl)
	 begin
		out[31] <= out[30];
		out[30] <= out[29];
		out[29] <= out[28];
		out[28] <= out[27];
		out[27] <= out[26];
		out[26] <= out[25];
		out[25] <= out[24];
		out[24] <= out[23];
		out[23] <= out[22];
		out[22] <= out[21];
		out[21] <= out[20];
		out[20] <= out[19];
		out[19] <= out[18];
		out[18] <= out[17];
		out[17] <= out[16];
		out[16] <= out[15];
		out[15] <= out[14];
		out[14] <= out[13];
		out[13] <= out[12];
		out[12] <= out[11];
		out[11] <= out[10];
		out[10] <= out[9];
		out[9] <= out[8];
		out[8] <= out[7];
		out[7] <= out[6];
		out[6] <= out[5];
		out[5] <= out[4];
		out[4] <= out[3];
		out[3] <= out[2];
		out[2] <= out[1];
		out[1] <= out[0];
		out[0] <= in0;
	 end
      else if (dshl)
	 begin
		out[31] <= out[29];
		out[30] <= out[28];
		out[29] <= out[27];
		out[28] <= out[26];
		out[27] <= out[25];
		out[26] <= out[24];
		out[25] <= out[23];
		out[24] <= out[22];
		out[23] <= out[21];
		out[22] <= out[20];
		out[21] <= out[19];
		out[20] <= out[18];
		out[19] <= out[17];
		out[18] <= out[16];
		out[17] <= out[15];
		out[16] <= out[14];
		out[15] <= out[13];
		out[14] <= out[12];
		out[13] <= out[11];
		out[12] <= out[10];
		out[11] <= out[9];
		out[10] <= out[8];
		out[9] <= out[7];
		out[8] <= out[6];
		out[7] <= out[5];
		out[6] <= out[4];
		out[5] <= out[3];
		out[4] <= out[2];
		out[3] <= out[1];
		out[2] <= out[0];
		out[1] <= in1;
		out[0] <= in0;
	 end
      else
         out <= out;

endmodule

module reg_32bit_B (out, in16, load, clear, clk, inc, dshl);
   parameter size=32, rVal=0;
   input [15:0] in16;
   input load, clear, clk, inc, dshl;
   output [(size-1):0] out;
   reg [(size-1):0]    out;

   always @(posedge clk)
      if (clear)
         out <= rVal;
      else if (load)
	 begin
		out[31] <= 1'b0;
		out[30] <= 1'b0;
		out[29] <= 1'b0;
		out[28] <= 1'b0;
		out[27] <= 1'b0;
		out[26] <= 1'b0;
		out[25] <= 1'b0;
		out[24] <= 1'b0;
		out[23] <= 1'b0;
		out[22] <= 1'b0;
		out[21] <= 1'b0;
		out[20] <= 1'b0;
		out[19] <= 1'b0;
		out[18] <= 1'b0;
		out[17] <= 1'b0;
		out[16] <= 1'b0;
		out[15] <= in16[15];
		out[14] <= in16[14];
		out[13] <= in16[13];
		out[12] <= in16[12];
		out[11] <= in16[11];
		out[10] <= in16[10];
		out[9] <= in16[9];
		out[8] <= in16[8];
		out[7] <= in16[7];
		out[6] <= in16[6];
		out[5] <= in16[5];
		out[4] <= in16[4];
		out[3] <= in16[3];
		out[2] <= in16[2];
		out[1] <= in16[1];
		out[0] <= in16[0];
	 end
      else if (inc)
         out <= out + 16'b1;
      else if (dshl)
	 begin
		out[31] <= out[29];
		out[30] <= out[28];
		out[29] <= out[27];
		out[28] <= out[26];
		out[27] <= out[25];
		out[26] <= out[24];
		out[25] <= out[23];
		out[24] <= out[22];
		out[23] <= out[21];
		out[22] <= out[20];
		out[21] <= out[19];
		out[20] <= out[18];
		out[19] <= out[17];
		out[18] <= out[16];
		out[17] <= out[15];
		out[16] <= out[14];
		out[15] <= out[13];
		out[14] <= out[12];
		out[13] <= out[11];
		out[12] <= out[10];
		out[11] <= out[9];
		out[10] <= out[8];
		out[9] <= out[7];
		out[8] <= out[6];
		out[7] <= out[5];
		out[6] <= out[4];
		out[5] <= out[3];
		out[4] <= out[2];
		out[3] <= out[1];
		out[2] <= out[0];
		out[1] <= 1'b0;
		out[0] <= 1'b0;
	 end
      else
         out <= out;

endmodule

module reg_32bit_X (out, in16, ldhi, ldlo, clear, clk, dshl);
   parameter size=32, rVal=0;
   input [15:0] in16;
   input ldhi, ldlo, clear, clk, dshl;
   output [(size-1):0] out;
   reg [(size-1):0]    out;

   always @(posedge clk)
      if (clear)
         out <= rVal;
      else if (ldhi)
	 begin
		out[31] <= in16[15];
		out[30] <= in16[14];
		out[29] <= in16[13];
		out[28] <= in16[12];
		out[27] <= in16[11];
		out[26] <= in16[10];
		out[25] <= in16[9];
		out[24] <= in16[8];
		out[23] <= in16[7];
		out[22] <= in16[6];
		out[21] <= in16[5];
		out[20] <= in16[4];
		out[19] <= in16[3];
		out[18] <= in16[2];
		out[17] <= in16[1];
		out[16] <= in16[0];
	 end
      else if (ldlo)
	 begin
		out[15] <= in16[15];
		out[14] <= in16[14];
		out[13] <= in16[13];
		out[12] <= in16[12];
		out[11] <= in16[11];
		out[10] <= in16[10];
		out[9] <= in16[9];
		out[8] <= in16[8];
		out[7] <= in16[7];
		out[6] <= in16[6];
		out[5] <= in16[5];
		out[4] <= in16[4];
		out[3] <= in16[3];
		out[2] <= in16[2];
		out[1] <= in16[1];
		out[0] <= in16[0];
	 end
      else if (dshl)
	 begin
		out[31] <= out[29];
		out[30] <= out[28];
		out[29] <= out[27];
		out[28] <= out[26];
		out[27] <= out[25];
		out[26] <= out[24];
		out[25] <= out[23];
		out[24] <= out[22];
		out[23] <= out[21];
		out[22] <= out[20];
		out[21] <= out[19];
		out[20] <= out[18];
		out[19] <= out[17];
		out[18] <= out[16];
		out[17] <= out[15];
		out[16] <= out[14];
		out[15] <= out[13];
		out[14] <= out[12];
		out[13] <= out[11];
		out[12] <= out[10];
		out[11] <= out[9];
		out[10] <= out[8];
		out[9] <= out[7];
		out[8] <= out[6];
		out[7] <= out[5];
		out[6] <= out[4];
		out[5] <= out[3];
		out[4] <= out[2];
		out[3] <= out[1];
		out[2] <= out[0];
		out[1] <= 1'b0;
		out[0] <= 1'b0;
	 end
      else
         out <= out;

endmodule

module reg_32bit_Y (out, in, load, clear, clk, dshl, in0, in1);
   parameter size=32, rVal=0;
   input [(size-1):0]  in;
   input load, clear, clk, dshl, in0, in1;
   output [(size-1):0] out;
   reg [(size-1):0]    out;

   always @(posedge clk)
      if (clear)
         out <= rVal;
      else if (load)
         out <= in;
      else if (dshl)
	 begin
		out[31] <= out[29];
		out[30] <= out[28];
		out[29] <= out[27];
		out[28] <= out[26];
		out[27] <= out[25];
		out[26] <= out[24];
		out[25] <= out[23];
		out[24] <= out[22];
		out[23] <= out[21];
		out[22] <= out[20];
		out[21] <= out[19];
		out[20] <= out[18];
		out[19] <= out[17];
		out[18] <= out[16];
		out[17] <= out[15];
		out[16] <= out[14];
		out[15] <= out[13];
		out[14] <= out[12];
		out[13] <= out[11];
		out[12] <= out[10];
		out[11] <= out[9];
		out[10] <= out[8];
		out[9] <= out[7];
		out[8] <= out[6];
		out[7] <= out[5];
		out[6] <= out[4];
		out[5] <= out[3];
		out[4] <= out[2];
		out[3] <= out[1];
		out[2] <= out[0];
		out[1] <= in1;
		out[0] <= in0;
	 end
      else
         out <= out;

endmodule