/* Greg Chabala
This file describes a four bit counter with
parallel load and synchronus load and clear 
inputs and a count enable input */

`timescale 1ns/100ps

module root_count (out, clear, clk);

	input           clear;  /* clear the counter to 4'h0 */
	input           clk;    /* clock input */
	output  	out;    /* output of counter */
	reg		out;

	reg     [3:0]   Q;      /* four bit register to hold count */

	/* State changes only on positive clock transitions */
	always @(posedge clk)
	begin
		if(clear == 1'b1) /* If clear is high, it has priority */
			Q <= 4'b0000;
		else  /* followed by count enable */
			Q <= Q + 4'b0001;
		if(Q == 4'b0000)
			out <= 1'b1;
		else
			out <= 1'b0;

	end

	/* Set the output to always be equal to the internal state */

endmodule