/* Greg Chabala */

`timescale 1ns/100ps

module rs_ff (out, set, reset, clk);
	input           set;   
	input           reset;  
	input           clk;   
	output          out;   

	reg             out;      

	/* State changes only on positive clock transitions */
	always @(negedge clk)
	begin
           if (set==1'b1 && reset==1'b0)
              out <= 1'b1;
           else if (set==1'b0 && reset==1'b1)
              out <= 1'b0;
           else if (set==1'b1 && reset==1'b1)
              out <= 1'bx;
           else
              out <= out;
        end


endmodule