//Greg Chabala
//ECE 483
//Simple Educational Processsor

`timescale 10ns/100ps

module sep(clk, reset, mem_bus, ram_rd_nwr, address);

input clk;
input reset;

wire [6:0] load_line;
wire [6:0] clr_line;
wire [6:0] reset_clr;
wire [6:0] inc_line;
wire cin;
wire flag_en;
wire ALU_sel;
wire [3:0] op_sel;
wire read_mem;
wire write_mem;
wire [2:0] bus_sel;
wire [15:0] IR_out;
wire [3:0] flag_out;
wire DR_zero;
wire [1:0] AC_lh;
wire SPdec;
wire clr_root, root_op, A_shl, A_inc, B_ld, B_inc, B_dshl;
wire X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, RC_inc, RC_zero, BY_out;

inout [15:0] mem_bus;
output ram_rd_nwr;
output [11:0] address;

data_unit DU(IR_out, flag_out, mem_bus, ram_rd_nwr, clk, load_line,
		 reset_clr, inc_line, read_mem, write_mem, ALU_sel, 
		op_sel, flag_en, cin, bus_sel, address, DR_zero, 
		AC_lh, SPdec, clr_root, root_op, A_shl, A_inc, B_ld, 
		B_inc, B_dshl, X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, 
		RC_inc, RC_zero, BY_out);

assign reset_clr[0] = clr_line[0] | reset;
assign reset_clr[1] = clr_line[1] | reset;
assign reset_clr[2] = clr_line[2] | reset;
assign reset_clr[3] = clr_line[3] | reset;
assign reset_clr[4] = clr_line[4] | reset;
assign reset_clr[5] = clr_line[5] | reset;
assign reset_clr[6] = clr_line[6] | reset;

control_unit CU(load_line, inc_line, clr_line, cin, flag_en, ALU_sel, 
		op_sel, read_mem, write_mem, bus_sel, IR_out, flag_out, 
		clk, 1'b0, reset, DR_zero, AC_lh, SPdec, clr_root, 
		root_op, A_shl, A_inc, B_ld, B_inc, B_dshl, X_ldhi, 
		X_ldlo, X_dshl, Y_ld, Y_dshl, RC_inc, RC_zero, BY_out);

endmodule

module control_unit(load_ctl, inc_ctl, clr_ctl, cin, flag_en, ALU_sel, op_sel, 
	read_mem, write_mem, bus_ctl, IR_out, flag_out, clk, R, reset, DR_zero, 
	AC_lh, SPdec, clr_root, root_op, A_shl, A_inc, B_ld, B_inc, B_dshl, 
	X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, RC_inc, RC_zero, BY_out);

	output [6:0] load_ctl;    //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR, 6-SP
	output [6:0] inc_ctl;
	output [6:0] clr_ctl;
	output read_mem;
	output write_mem;
	output [2:0] bus_ctl;
	output cin;
	output flag_en;
	output ALU_sel;
	output [3:0] op_sel;
	output SPdec;
	output clr_root, root_op, A_shl, A_inc, B_ld, B_inc, B_dshl; 
	output X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, RC_inc;

	//flags 0:  overflow
	//      1:  carry
	//      2:  sign
	//      3:  zero

	input [15:0] IR_out;
	input [3:0] flag_out;
	input clk;
	input R;
	input reset;
	input DR_zero;
	input [1:0] AC_lh;
	input RC_zero, BY_out;

	wire [4:0] SC_out;
	wire SC_clr;
	wire SC_inc;
	wire ld9;
	wire [7:0] D_input;
	wire [31:0] T_input;

	seq_counter SC(SC_out, SC_clr | reset, SC_inc, clk, ld9);
	a3to8_decoder D1(D_input, IR_out[14:12]);
	a5to32_decoder D2(T_input, SC_out);
	control_logic CTL(load_ctl, inc_ctl, clr_ctl, cin, flag_en, ALU_sel, op_sel,
			 read_mem, write_mem, SC_clr, SC_inc, bus_ctl, IR_out[11:0],
			 IR_out[15], D_input, T_input, flag_out, R, DR_zero, clk,
			 AC_lh, reset, SPdec, ld9, clr_root, root_op, A_shl, A_inc, 
			 B_ld, B_inc, B_dshl, X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, 
			 RC_inc, RC_zero, BY_out);

endmodule


module control_logic(load_ctl, inc_ctl, clr_ctl, cin, flag_en, ALU_sel, op_sel,
		 read_mem, write_mem, SC_clr, SC_inc, bus_ctl, ad, I, D, T, flag, 
		R, DR_zero, clk, AC_lh, reset, SPdec, ld9, clr_root, root_op, A_shl, 
		A_inc, B_ld, B_inc, B_dshl, X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, 
		RC_inc, RC_zero, BY_out);

	output [6:0] load_ctl;    //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR, 6-SP
	output [6:0] inc_ctl;
	output [6:0] clr_ctl;
	output read_mem;
	output write_mem;
	output [2:0] bus_ctl;
	output SC_clr, SC_inc;
	output cin;
	output flag_en;
	output ALU_sel;
	output [3:0] op_sel;
	output SPdec;
	output ld9;
	output clr_root, root_op, A_shl, A_inc, B_ld, B_inc, B_dshl; 
	output X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, RC_inc;

	input [11:0] ad;
	input I;
	input [7:0] D;
	input [31:0] T;
	input [3:0] flag;
	input R;
	input DR_zero;
	input clk;
	input [1:0] AC_lh;
	input reset;
	input RC_zero, BY_out;

	wire E_out;
	wire E_in;
	wire E_load;
	wire E_clr;
	wire E_comp;

	flipflop E(E_out, E_in, E_load, E_clr, clk, E_comp);

	//flags 0:  overflow
	//      1:  carry
	//      2:  sign
	//      3:  zero

	assign read_mem = (~R & T[1]) | (~D[7] & I & T[3]) | 
			((D[0] | D[1] | D[2] | D[6]) & T[4]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] &  ad[9] &  ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[7] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);

	assign write_mem = (R & T[1]) | (D[6] & T[6]) | (T[4] & (D[3] | D[5])) |
		(T[4] & D[7] & ~I & ~ad[4] &  ad[5] &  ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[17] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);

	assign SC_clr = ((D[0] | D[1] | D[2] | D[5]) & T[5]) | 
			(D[7] & T[6] & ~(ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11])) | 
			(D[6] & T[6]) | 
			(R & T[2]) | 
			((D[3] | D[4]) & T[4]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] &  ad[5] &  ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[6] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[17] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign SC_inc = 1'b1;

	assign ld9 = (T[15] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11] & ~RC_zero);

	assign clr_root = (T[6] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign root_op = (T[16] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign A_shl = (T[10] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign A_inc = (T[11] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11] & BY_out);
	assign B_ld = (T[12] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign B_inc = (T[7] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
			(T[14] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign B_dshl = (T[13] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign X_ldhi = (T[8] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign X_ldlo = (T[6] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign X_dshl = (T[10] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign Y_ld = (T[11] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11] & BY_out);
	assign Y_dshl = (T[9] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign RC_inc = (T[14] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);

	assign SPdec = (T[4] & D[7] & ~I &  ad[5] &  ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
			(T[17] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);

	assign cin = (T[5] & D[7] & ~I & ad[11] & ad[10] & ~ad[9] & ~ad[8] & ~ad[7]);
	assign flag_en = 1'b1;
	assign ALU_sel = (D[7] & ~I & T[3] & (ad[7] | ad[6] | ad[9])) |
				(T[5] & D[7] & ~I & ad[11] & ad[10]);

	assign load_ctl[0] = ((~R) & (T[0] | T[2])) | ((~D[7]) & I & T[3]) |
		(T[3] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] &  ad[9] &  ad[10] & ~ad[11]) |
		(T[3] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(T[3] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[3] & D[7] & ~I & ~ad[4] &  ad[5] &  ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[6] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign inc_ctl[0] = D[5] & T[4];
	assign clr_ctl[0] = R & T[0];

	assign load_ctl[1] = (D[4] & T[4]) | (D[5] & T[5]);
	assign inc_ctl[1] = (~R & T[1]) | (R & T[2]) | (DR_zero & D[6] & T[6]) | 
				((D[7] & ~I & T[3]) & 
		((~AC_lh[1] & ad[4] & ~ad[5] & ~ad[6] & ~ad[10] & ~ad[3]) | 
		(flag[2] & ad[3] & ~ad[4] & ~ad[2] & ~ad[5]) |
		(flag[3] & ad[2] & ~ad[3] & ~ad[1] & ~ad[4]) |
		(~E_out & ad[1] & ~ad[2] & ~ad[3] & ~ad[4]))) |
		(T[4] & D[7] & ~I & ~ad[8] & ad[9] & ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[8] & ~ad[9] & ad[10] & ad[11]) |
		(flag[0] & T[3] & ~I & D[7] & ad[9] & ad[8] & ~ad[10] & ~ad[11] & ~ad[7] & ~ad[6] & ~ad[5]) |
		(~(flag[2] ^ flag[0]) & ~flag[3] & T[3] & ~I & D[7] & ad[8] & ad[7] &
			 ~ad[11] & ~ad[10] & ~ad[9] & ~ad[6] & ~ad[5]) |
		(T[4] & D[7] & ~I &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]);
	assign clr_ctl[1] = R & T[1];

	assign load_ctl[2] = ((D[0] | D[1] | D[2] | D[6] | (D[7] & ~I & ad[9] & ad[10]) | 
				(D[7] & ~I & ad[11] & ad[10])) & T[4]) |
		(T[5] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[7] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[16] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign inc_ctl[2] = D[6] & T[5];
	assign clr_ctl[2] = 1'b0;

	assign load_ctl[3] = (D[7] & ~I & T[3] & 
		((ad[7] & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) | 
		(ad[6] & ~ad[4] & ~ad[5] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) | 
		(ad[9] & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[8] & ~ad[7] & ~ad[10] & ~ad[11]))) |
				((D[0] | D[1] | D[2]) & T[5]) |
		(D[7] & ~I & T[5] & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] &  ad[9] &  ad[10] & ~ad[11]) |
		(D[7] & ~I & T[5] & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(D[7] & ~I & T[6] &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]);
	assign inc_ctl[3] = 
		(D[7] & ~I & T[3] & ~ad[11] & ~ad[10] & ~ad[9] & ~ad[8] & ~ad[7] & ~ad[6] &  ad[5] & ~ad[4]);
	assign clr_ctl[3] = 
		(D[7] & ~I & T[3] &  ad[11] & ~ad[10] & ~ad[9] & ~ad[8] & ~ad[7] & ~ad[6] & ~ad[5] & ~ad[4]);

	assign load_ctl[4] = (~R & T[1]);
	assign inc_ctl[4] = 1'b0;
	assign clr_ctl[4] = 1'b0;

	assign load_ctl[5] = (R & T[0]);
	assign inc_ctl[5] = 1'b0;
	assign clr_ctl[5] = 1'b0;

	assign load_ctl[6] = 
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]);
	assign inc_ctl[6] = 
		(T[3] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[3] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[5] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign clr_ctl[6] = 1'b0;

	assign op_sel[0] = (D[7] & (~I) & T[3] & ad[9] & ~ad[8] & ~ad[7] & ~ad[10] & ~ad[11]) |
			 (T[5] & D[7] & (~I) & ad[11] & ad[10] & ~ad[9] & ~ad[8] & ~ad[7]);
	assign op_sel[1] = (D[2] & T[5]) |
			 (D[7] & ~I & T[3] & ad[9] & ~ad[8] & ~ad[7] & ~ad[10] & ~ad[11] & ~ad[4]) |
			 (D[7] & ~I & ad[9] & ad[10] & T[5] & ~ad[8] & ~ad[7] & ~ad[11] & ~ad[4]) |
		(T[6] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]);
	assign op_sel[2] = (D[0] & T[5]) | 
			(D[7] & (~I) & T[3] & ((ad[6] & ~ad[9] & ~ad[10] & ~ad[11] & ~ad[7] & ~ad[8]) |
			(ad[9] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[10] & ~ad[11])));
	assign op_sel[3] = D[7] & (~I) & T[3] & ((ad[7] & ~ad[6] & ~ad[8]) |
			 (ad[6] & ~ad[7] & ~ad[5] & ~ad[8]));

	assign bus_ctl[0] = (D[5] & T[5]) | (D[6] & T[6]) | ((~R) & (T[2] | T[1])) | 
				(~D[7] & I & T[3]) | 
				((D[0] | D[1] | D[2] | D[4] | D[6]) & T[4]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] &  ad[9] &  ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(T[5] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[7] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[17] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign bus_ctl[1] = T[0] | T[1] | (D[6] & T[6]) | ((D[0] | D[1] | D[2] | D[5] | D[6]) & T[4]) | 
				(~D[7] & I & T[3]) | 
		(T[3] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] &  ad[9] &  ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] &  ad[9] &  ad[10] & ~ad[11]) |
		(T[3] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(T[3] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[7] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[17] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);
	assign bus_ctl[2] = ((D[0] | D[1] | D[2] | D[3] | D[6]) & T[4]) | T[1] | (~R & T[2]) |
				 (~D[7] & I & T[3]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] &  ad[9] &  ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] &  ad[10] &  ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] & ~ad[5] &  ad[6] &  ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[4] & D[7] & ~I & ~ad[4] &  ad[5] &  ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I &  ad[4] &  ad[5] & ~ad[6] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10] & ~ad[11]) |
		(T[5] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]) |
		(T[7] & D[7] & ~I & ad[1] & ad[2] & ad[3] & ad[4] & ad[5] &
				  ad[6] & ad[7] & ad[8] & ad[9] & ad[10] & ad[11]);

	assign E_clr = (D[7] & ~I & T[3] & ad[10] & ~ad[11] & ~ad[9]) | reset;
	assign E_comp = (D[7] & ~I & T[3] & ad[8] & ~ad[7] & ~ad[9] & ~ad[10] & ~ad[11]);
	assign E_load = (D[1] & T[5]) | (D[7] & ~I & T[3] &
			 ((ad[7] & ~ad[6] & ~ad[5] & ~ad[8] & ~ad[9]) | 
			 (ad[6] & ~ad[5] & ~ad[7] & ~ad[8] & ~ad[9] & ~ad[10])));
	assign E_in = (D[1] & T[5])? flag[1] : 
			(D[7] & ~I & T[3] & ad[7] & ~ad[6] & ~ad[8])? AC_lh[0] : 
			(D[7] & ~I & T[3] & ad[6] & ~ad[5] & ~ad[7])? AC_lh[1] : 1'bz;

endmodule

module a3to8_decoder(out, sel);

	input	[2:0]	sel;
	output	[7:0]	out;
	reg	[7:0]	out;

	always @(sel)
		case (sel)
		    3'b000 :	out <= 8'b00000001;
		    3'b001 :	out <= 8'b00000010;
		    3'b010 :	out <= 8'b00000100;
		    3'b011 :	out <= 8'b00001000;
		    3'b100 :	out <= 8'b00010000;
		    3'b101 :	out <= 8'b00100000;
		    3'b110 :	out <= 8'b01000000;
		    3'b111 :	out <= 8'b10000000;
		    default :	out <= 8'b00000001;
		endcase
endmodule

module a4to16_decoder(out, sel);

	input	[3:0]	sel;
	output	[15:0]	out;
	reg	[15:0]	out;

	always @(sel)
		case (sel)
		    4'b0000 :	out <= 16'b0000000000000001;
		    4'b0001 :	out <= 16'b0000000000000010;
		    4'b0010 :	out <= 16'b0000000000000100;
		    4'b0011 :	out <= 16'b0000000000001000;
		    4'b0100 :	out <= 16'b0000000000010000;
		    4'b0101 :	out <= 16'b0000000000100000;
		    4'b0110 :	out <= 16'b0000000001000000;
		    4'b0111 :	out <= 16'b0000000010000000;
		    4'b1000 :	out <= 16'b0000000100000000;
		    4'b1001 :	out <= 16'b0000001000000000;
		    4'b1010 :	out <= 16'b0000010000000000;
		    4'b1011 :	out <= 16'b0000100000000000;
		    4'b1100 :	out <= 16'b0001000000000000;
		    4'b1101 :	out <= 16'b0010000000000000;
		    4'b1110 :	out <= 16'b0100000000000000;
		    4'b1111 :	out <= 16'b1000000000000000;
		    default :	out <= 16'b0000000000000001;
		endcase
endmodule

module a5to32_decoder(out, sel);

	input	[4:0]	sel;
	output	[31:0]	out;
	reg	[31:0]	out;

	always @(sel)
		case (sel)
		    5'b00000 :	out <= 32'b00000000000000000000000000000001;
		    5'b00001 :	out <= 32'b00000000000000000000000000000010;
		    5'b00010 :	out <= 32'b00000000000000000000000000000100;
		    5'b00011 :	out <= 32'b00000000000000000000000000001000;
		    5'b00100 :	out <= 32'b00000000000000000000000000010000;
		    5'b00101 :	out <= 32'b00000000000000000000000000100000;
		    5'b00110 :	out <= 32'b00000000000000000000000001000000;
		    5'b00111 :	out <= 32'b00000000000000000000000010000000;
		    5'b01000 :	out <= 32'b00000000000000000000000100000000;
		    5'b01001 :	out <= 32'b00000000000000000000001000000000;
		    5'b01010 :	out <= 32'b00000000000000000000010000000000;
		    5'b01011 :	out <= 32'b00000000000000000000100000000000;
		    5'b01100 :	out <= 32'b00000000000000000001000000000000;
		    5'b01101 :	out <= 32'b00000000000000000010000000000000;
		    5'b01110 :	out <= 32'b00000000000000000100000000000000;
		    5'b01111 :	out <= 32'b00000000000000001000000000000000;
		    5'b10000 :	out <= 32'b00000000000000010000000000000000;
		    5'b10001 :	out <= 32'b00000000000000100000000000000000;
		    5'b10010 :	out <= 32'b00000000000001000000000000000000;
		    5'b10011 :	out <= 32'b00000000000010000000000000000000;
		    5'b10100 :	out <= 32'b00000000000100000000000000000000;
		    5'b10101 :	out <= 32'b00000000001000000000000000000000;
		    5'b10110 :	out <= 32'b00000000010000000000000000000000;
		    5'b10111 :	out <= 32'b00000000100000000000000000000000;
		    5'b11000 :	out <= 32'b00000001000000000000000000000000;
		    5'b11001 :	out <= 32'b00000010000000000000000000000000;
		    5'b11010 :	out <= 32'b00000100000000000000000000000000;
		    5'b11011 :	out <= 32'b00001000000000000000000000000000;
		    5'b11100 :	out <= 32'b00010000000000000000000000000000;
		    5'b11101 :	out <= 32'b00100000000000000000000000000000;
		    5'b11110 :	out <= 32'b01000000000000000000000000000000;
		    5'b11111 :	out <= 32'b10000000000000000000000000000000;
		    default :	out <= 32'b00000000000000000000000000000001;
		endcase
endmodule

module seq_counter (out, clear, cnt, clk, ld9);
        //input   [3:0]   in;     /* parallel load input */
	//input           load;   /* load parallel input */
	input           clear;  /* clear the counter to 4'h0 */
	input           cnt;    /* count enable input */
	input           clk;    /* clock input        */
	input		ld9;	/* load 9             */
	output  [4:0]   out;    /* output of counter  */

	reg     [4:0]   Q;      /* four bit register to hold count */

	/* State changes only on positive clock transitions */
	always @(negedge clk)
	begin
		if(clear == 1'b1) /* If clear is high, it has priority */
			Q <= 5'b00000;
		//else if(load == 1'b1) /* load has the next highest */
		//	Q <= in;
		else if(ld9 == 1'b1) /* ld9 has the next highest */
			Q <= 5'b01001;
		else if(cnt == 1'b1) /* followed by count enable */
			Q <= Q + 5'b00001;
		else
			Q <= Q;
	end

	/* Set the output to always be equal to the internal state */
	assign out = Q;

endmodule

module flipflop(out, in, load, clear, clk, comp);
   input in;
   input load, clear, clk, comp;
   output out;
   reg out;

   always @(posedge clk)
      if (clear)
         out <= 1'b0;
      else if (load)
         out <= in;
      else if (comp)
         out <= ~out;
      else
         out <= out;

endmodule


module data_unit(IR_out, flag_out, mem_bus, ram_rd_nwr, clk, load_line, clr_line, inc_line, read, write, ALU_sel, op_sel, flag_en, cin, bus_sel, address_out, DR_zero, AC_lh, SPdec, clr_root, root_op, A_shl, A_inc, B_ld, B_inc, B_dshl, X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, RC_inc, RC_zero, BY_out);

output [3:0] flag_out;
output [15:0] IR_out;
input [15:0] mem_bus;
output ram_rd_nwr;
input clk;
input read, write;

wire [15:0] MEM_out;
wire [15:0] bus;            //no one likes to ride the bus -Socrates
wire [15:0] bus2;
wire [11:0] AR_out;
wire [11:0] SP_out;
wire [11:0] PC_out;
wire [15:0] DR_out;
wire [15:0] DPU_out;
wire [15:0] TR_out;
input [6:0] load_line;      //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR, 6-SP
input [6:0] clr_line;       //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR, 6-SP
input [6:0] inc_line;       //0-AR, 1-PC, 2-DR, 3-AC, 4-IR, 5-TR, 6-SP
input clr_root;
input SPdec;
output [11:0] address_out;
output DR_zero;
output [1:0] AC_lh;

input A_shl, A_inc, B_ld, B_inc, B_dshl, X_ldhi, X_ldlo, X_dshl, Y_ld, Y_dshl, RC_inc;
output RC_zero, BY_out;

//extra lines
input cin;
input flag_en;
input ALU_sel;
input [3:0] op_sel;
input [2:0] bus_sel;
input root_op;

wire [15:0] A_out;

reg_12bit_sp SP(SP_out, bus[11:0], load_line[6], clr_line[6], clk, inc_line[6], SPdec);
reg_12bit    AR(AR_out, bus[11:0], load_line[0], clr_line[0], clk, inc_line[0], 1'b0);
reg_12bit_pc PC(PC_out, bus[11:0], load_line[1], clr_line[1], clk, inc_line[1]);
reg_16bit    DR(DR_out, bus2, load_line[2], clr_line[2], clk, inc_line[2]);
reg_16bit    IR(IR_out, bus, load_line[4], clr_line[4], clk, inc_line[4]);
reg_16bit    TR(TR_out, bus, load_line[5], clr_line[5], clk, inc_line[5]);
sep_dpu     DPU(DPU_out, flag_out, DR_out, op_sel, cin, clk, flag_en, load_line[3], clr_line[3], inc_line[3], ALU_sel);
mux_8to1_16bit THE_BUS(bus, bus_sel, SP_out, AR_out, PC_out, DR_out, DPU_out, IR_out, TR_out, MEM_out);

mux_2to1_16bit ROOT_ANS(bus2, root_op, bus, A_out);

wire [31:0] B_out, X_out, Y_out, YB_out;

reg_16bit_A A(A_out, clr_root, clk, A_inc, A_shl);
reg_32bit_B B(B_out, A_out, B_ld, clr_root, clk, B_inc, B_dshl);
reg_32bit_X X(X_out, DR_out, X_ldhi, X_ldlo, 1'b0, clk, X_dshl);
reg_32bit_Y Y(Y_out, YB_out, Y_ld, clr_root, clk, Y_dshl, X_out[14], X_out[15]);
root_count RC(RC_zero, clr_root, clk, RC_inc);
subtract_32bit YB(YB_out, Y_out, B_out);
smaller_than SMTH(BY_out, B_out, Y_out, clk);

assign DR_zero = ~&DR_out;

assign AC_lh[0] = DPU_out[0];
assign AC_lh[1] = DPU_out[15];

memory_unit MEM(MEM_out, address_out, mem_bus, bus, AR_out, read, write, ram_rd_nwr);

endmodule


//DPU unit

module sep_dpu(dpu_out, flag_out, data_in, sel, cin, clk, flag_en, ac_en, acclr, AC_inc, ALU_sel);
           output  [15:0] dpu_out;               // DPU output
           output  [3:0]  flag_out;              // flag outputs
           input   [15:0] data_in;               // data input
           input   [3:0]  sel;                   // operation selection
           input          cin;                   // carry in
           input          clk;                   // clock input
           input          flag_en;               // flag enable
           input          ac_en;                 // ac enable
           input          acclr;                 // ac clear
           input          AC_inc;                // AC increment
           input          ALU_sel;		 // selects ALU inputs

      wire [15:0] Y;
      wire [15:0] ALU_A;
      wire [15:0] ALU_B;
      wire cout15;
      wire rightout, leftout;
      wire [3:0] flag_lines;

mux_2to1_16bit A_in(ALU_A, ALU_sel, data_in, dpu_out);
mux_2to1_16bit B_in(ALU_B, ALU_sel, dpu_out, data_in);
      

//flags 0:  overflow
//      1:  carry
//      2:  sign
//      3:  zero


sep_alu my_alu(Y, flag_lines[1], cout15, rightout, leftout, ALU_A, ALU_B, sel, cin, flag_out[1], flag_out[1]);
reg_16bit AC(dpu_out, Y, ac_en, acclr, clk, AC_inc);
reg_4bit FLAG(flag_out, flag_lines, flag_en, 1'b0, clk, 1'b0);
assign flag_lines[0] = flag_lines[1] ^ cout15;
assign flag_lines[2] = dpu_out[15];
assign flag_lines[3] = ~&dpu_out;

endmodule

module root_count (out, clear, clk, inc);

	input           clear;  /* clear the counter to 4'h0 */
	input           clk;    /* clock input */
	input 		inc;
	output  	out;    /* output of counter */
	reg		out;

	reg     [3:0]   Q;      /* four bit register to hold count */

	/* State changes only on positive clock transitions */
	always @(posedge clk)
	begin
		if(clear == 1'b1) /* If clear is high, it has priority */
			Q <= 4'b0000;
		else if (inc)  /* followed by count enable */
			Q <= Q + 4'b0001;
		else
			Q <= Q;
		if(Q == 4'b0000)
			out <= 1'b1;
		else
			out <= 1'b0;

	end

	/* Set the output to always be equal to the internal state */

endmodule

module adder_32bit(sum, cout, in1, in2, cin);

        input   [31:0]  in1;
        input   [31:0]  in2;
        input           cin;

        output  [31:0]  sum;
        output          cout;

        wire    [31:0]  cvect;

        adder_1bit u0(sum[0], cvect[0], in1[0], in2[0], cin);
        adder_1bit u1(sum[1], cvect[1], in1[1], in2[1], cvect[0]);
        adder_1bit u2(sum[2], cvect[2], in1[2], in2[2], cvect[1]);
        adder_1bit u3(sum[3], cvect[3], in1[3], in2[3], cvect[2]);
        adder_1bit u4(sum[4], cvect[4], in1[4], in2[4], cvect[3]);
        adder_1bit u5(sum[5], cvect[5], in1[5], in2[5], cvect[4]);
        adder_1bit u6(sum[6], cvect[6], in1[6], in2[6], cvect[5]);
        adder_1bit u7(sum[7], cvect[7], in1[7], in2[7], cvect[6]);
        adder_1bit u8(sum[8], cvect[8], in1[8], in2[8], cvect[7]);
        adder_1bit u9(sum[9], cvect[9], in1[9], in2[9], cvect[8]);
        adder_1bit u10(sum[10], cvect[10], in1[10], in2[10], cvect[9]);
        adder_1bit u11(sum[11], cvect[11], in1[11], in2[11], cvect[10]);
        adder_1bit u12(sum[12], cvect[12], in1[12], in2[12], cvect[11]);
        adder_1bit u13(sum[13], cvect[13], in1[13], in2[13], cvect[12]);
        adder_1bit u14(sum[14], cvect[14], in1[14], in2[14], cvect[13]);
        adder_1bit u15(sum[15], cvect[15], in1[15], in2[15], cvect[14]);
        adder_1bit u16(sum[16], cvect[16], in1[16], in2[16], cvect[15]);
        adder_1bit u17(sum[17], cvect[17], in1[17], in2[17], cvect[16]);
        adder_1bit u18(sum[18], cvect[18], in1[18], in2[18], cvect[17]);
        adder_1bit u19(sum[19], cvect[19], in1[19], in2[19], cvect[18]);
        adder_1bit u20(sum[20], cvect[20], in1[20], in2[20], cvect[19]);
        adder_1bit u21(sum[21], cvect[21], in1[21], in2[21], cvect[20]);
        adder_1bit u22(sum[22], cvect[22], in1[22], in2[22], cvect[21]);
        adder_1bit u23(sum[23], cvect[23], in1[23], in2[23], cvect[22]);
        adder_1bit u24(sum[24], cvect[24], in1[24], in2[24], cvect[23]);
        adder_1bit u25(sum[25], cvect[25], in1[25], in2[25], cvect[24]);
        adder_1bit u26(sum[26], cvect[26], in1[26], in2[26], cvect[25]);
        adder_1bit u27(sum[27], cvect[27], in1[27], in2[27], cvect[26]);
        adder_1bit u28(sum[28], cvect[28], in1[28], in2[28], cvect[27]);
        adder_1bit u29(sum[29], cvect[29], in1[29], in2[29], cvect[28]);
        adder_1bit u30(sum[30], cvect[30], in1[30], in2[30], cvect[29]);
        adder_1bit u31(sum[31], cvect[31], in1[31], in2[31], cvect[30]);

        assign cout = cvect[31];

endmodule

module subtract_32bit(sum, in1, in2);

        input   [31:0]  in1;
        input   [31:0]  in2;

        output  [31:0]  sum;

	wire cout;

	adder_32bit ADD(sum, cout, in1, ~in2, 1'b1);


endmodule

module smaller_than(sum, in1, in2, clk);

        input   [31:0]  in1;
        input   [31:0]  in2;
	input clk;

        output   sum;
	reg sum;

	always @(clk)
	begin
		if(in1 < in2)
			sum <= 1'b1;
		else
			sum <= 1'b0;
	end


endmodule