/*****************************************************

File: sep_alu_tb.v
Author: Jeremy Wood
Date: 6-8-04

Desc: This is the test bench for the ALU 

modified 9-18-04  Added driveable left and right 
                  shift inputs
*****************************************************/

`timescale 1ns/100ps

module sep_alu_tb;

        reg     [15:0]  A;                      // A Input
        reg     [15:0]  B;                      // B Input
        reg     [3:0]   s;                      // Operation select input
        reg             cin;                    // Carry input
        reg             rightIn;                // Right Input from the shift operations
        reg             leftIn;                 // Left Input from the shift operations
        
        wire    [15:0]  Y;                      // Y Ouput
        wire            cout16, cout15;          // Carry Outputs
        wire            rightout, leftout;       // Shift Outputs
        
        integer         fid;                    // File handle for output file
        
        // Invoke an instance of the test bench
        sep_alu         alu(Y, cout16, cout15, rightout, leftout, A, B, s, cin, rightIn, leftIn);
        
        initial begin
                
                fid = $fopen("./sep_alu.out");
                $fmonitor(fid, $time, " s=%b, cin=%b, A=%h, B=%h, Y=%h",
                        s, cin, A, B, Y );
                
                $dumpfile("./sep_alu.dmp");
                $dumpvars(6, sep_alu_tb);
                
                A <= 16'habcd;
                B <= 16'h1234;
                rightIn <= 1'b0;
                leftIn <= 1'b0;
                                
                // Addition
                #20 s <= 4'b0000;
                cin <= 1'b0;
                
                // Addition with Carry
                #20 cin <= 1'b1;
                
                // Subtract with Borrow
                #20 s <= 4'b0001;
                cin <= 1'b0;
                
                // Subtraction
                #20 cin <= 1'b1;
                
                // Transfer A
                #20 s <= 4'b0010;
                cin <= 1'b0;
                
                // Increment
                #20 cin <=1'b1;
                
                // Decrement A
                #20 s <= 4'b0011;
                cin <= 1'b0;
                
                // Transfer A
                #20 cin <= 1'b1;
                
                // AND
                #20 s <= 4'b0100;
                
                // OR
                #20 s <= 4'b0101;
                
                // XOR
                #20 s <= 4'b0110;
                
                // Complement A
                #20 s <= 4'b0111;
                
                // Shift right A into F
                #20 s <= 4'b1000;
                
                // Shift left A into F
                #20 s <= 4'b1100;
                
                // 42 + -13
                #20 A <= 16'd42;
                    B <= 16'b1111111111110011;
                    s <= 4'd0;

                // -42 - -13
                #20 A <= 16'b1111111111010110;
                    B <= 16'b1111111111110011;
                    s <= 4'd1;

                // 70 + 80
                #20 A <= 16'd70;
                    B <= 16'd80;
                    s <= 4'd0;

                // -70 + -80
                #20 A <= 16'b1111111110111010;
                    B <= 16'b1111111110110000;

                // Clear signals for Simvision
                #20 A <= 16'h0000;
                    B <= 16'h0000;
                    
                #20 $finish;
        end
endmodule