//Greg Chabala
//DPU unit

module sep_dpu(dpu_out, flag_out, data_in, sel, cin, clk);
           output  [15:0] dpu_out;               // DPU output
           output  [3:0]  flag_out;              // flag outputs
           input   [15:0] data_in;               // data input
           input   [3:0]  sel;                   // operation selection
           input          cin;                   // carry in
           input          clk;                   // clock input

      wire [15:0] Y;
      wire cout15;
      wire rightout, leftout;
      wire [3:0] flag_lines;
      

//flags 0:  overflow
//      1:  carry
//      2:  sign
//      3:  zero


sep_alu my_alu(Y, flag_lines[1], cout15, rightout, leftout, data_in, 
dpu_out, sel, cin, 1'b0, 1'b0);

reg_16bit AC(dpu_out, Y, 1'b1, 1'b0, clk);

reg_4bit FLAG(flag_out, flag_lines, 1'b1, 1'b0, clk);

xor U1(flag_lines[0], flag_lines[1], cout15);   //sets overflow

assign flag_lines[2] = Y[15];

and U2(flag_lines[3], ~Y[0], ~Y[1], ~Y[2], ~Y[3], ~Y[4], ~Y[5], ~Y[6], 
~Y[7], ~Y[8], ~Y[9], ~Y[10], ~Y[11], ~Y[12], ~Y[13], ~Y[14], ~Y[15]);

endmodule