/*********************************************************
*
* File: sep_dpu_tb.v
* Author: Jeremy Wood
* Date: 10-01-04
*
* Desc: This is the test bench for the DPU. The DPU 
*	consists of the ALU, Accumulator, and the Flag
*	Register. 
*
**********************************************************/

`timescale 1ns/100ps


// This defines the testbench for the DPU

// ** NOTE** The mux select lines for the ALU are also tied
// to the E bit mux. 

module sep_dpu_tb;

	reg	[15:0]	data_in;			// A input
	reg	[3:0]	sel;			// ALU and E bit control signals
	reg		cin;			// Carry In
	reg		clk;			// Common clock

	wire	[15:0]	dpu_out;		// Output from the DPU (also the AC Output)
	wire		cout;			// The carry out
	wire	[3:0]	flag_out;		// Output from the status register

	integer		fid;			// File ID to dump the monitor 

	// Initialize the DPU module

	sep_dpu		dpu(dpu_out, flag_out, data_in, sel, cin, clk);

	// Setup the Clock

	initial begin
		clk = 1'b0;
		forever #10 clk <= ~clk;
	end

	// Simulate the DPU

	initial begin

		fid = $fopen("./sep_dpu.out");

		$fmonitor(fid, $time, " data_in=%h, sel=%b, cin=%b, dpu_out=%h, flag_out=%b", 
			data_in, sel, cin, dpu_out, flag_out);

		$dumpfile("./sep_dpu.dmp");
		$dumpvars(4, sep_dpu_tb);

		// Set the initial A input and control signals for the ALU to perform a transfer

		#20 data_in	<= 16'hFFFF;
		    sel		<= 4'b0010;
		    cin		<= 1'b0;

		// A + AC (The B input)

		#20 data_in	<= 16'h0001;
		    sel		<= 4'b0000;
		
		// A + AC again

		#20 data_in	<= 16'h8000;

		// A - AC

		#20 data_in	<= 16'hFFFF;
		    sel		<= 4'b0001;
		    cin 	<= 1'b1;

		// A + AC

		#20 data_in	<= 16'h0001;
		    sel 	<= 4'b0000;
		    cin 	<= 1'b0;

		// A - AC

		#20 data_in	<= 16'hFFFE;
		    sel 	<= 4'b0001;
		    cin 	<= 1'b1;

		// A - AC

		#20 data_in	<= 16'hFFFD;
		
		// Clear signals for simvision

		#20 data_in	<= 16'h0000;
		    sel		<= 4'b0000;
		    cin 	<= 1'b0;

		#20 $finish;
	end

endmodule