//Greg Chabala
//SEP testbench

`timescale 10ns/100ps

module sep_tb;

	reg clk;
	reg reset;

	wire [15:0] mem_bus;
	wire ram_rd_nwr;
	wire [11:0] address;

	integer		fid;

	sep PROC(clk, reset, mem_bus, ram_rd_nwr, address);
	RAM_4096x16 ram(mem_bus, address, ram_rd_nwr);

	initial begin
		clk = 1'b0;
		forever #10 clk <= ~clk;
	end

initial begin

	fid = $fopen("./sep.out");

	$fmonitor(fid, $time, " clk=%b, reset=%b", clk, reset);

	$dumpfile("./sep.dmp");
	$dumpvars(6, sep_tb);

	#15 reset <= 1'b1;
	#25 reset <= 1'b0;

	#30000 $finish;

end

endmodule