//Greg Chabala
//ECE 483 Lab 2
//sequenital circuit 'up-down counter'

`timescale 1ns/100ps

module seqlckt (a_out, b_out, E, x, clk);
   output a_out;
   output b_out;
   input E;
   input x;
   input clk;

   rs_ff A (a_out, set_a, res_a, clk);
   rs_ff B (b_out, set_b, res_b, clk);

//always @(posedge clk) begin
   and (set_b, E, ~b_out);
   and (res_b, E, b_out);
   and (w1, E, ~x, ~a_out, ~b_out);
   and (w2, E, x, ~a_out, b_out);
   or (set_a, w1, w2);
   and (w3, E, x, a_out, b_out);
   and (w4, E, ~x, a_out, ~b_out);
   or (res_a, w3, w4);
//end
endmodule