//Greg Chabala
//ECE 483 lab 2
//seq ckt testbench

`timescale 1ns/100ps

module seqlckt_tb;

   reg in_E;
   reg in_x;
   reg clock;
   wire out_A;
   wire out_B;
   integer fid;

   seqlckt test(out_A, out_B, in_E, in_x, clock);


initial begin
   clock = 1'b0;
   forever #5 clock <= ~clock;
end

   initial begin

   fid = $fopen("./seqlckt.out");
$fmonitor(fid, $time, " A = %b, B = %b, E = %b, x = %b", out_A, out_B, in_E, in_x);
$dumpfile("./seqlckt.dmp");
$dumpvars(2, seqlckt_tb);

in_E <= 1'b0;
in_x <= 1'b0;
#10 in_x <= ~in_x;
#10 in_E <= ~in_E;
#40 in_x <= ~in_x;
#40 in_x <= ~in_x;
#10 in_E <= 1'b0;
#10 in_x <= ~in_x;
#10 in_x <= ~in_x; in_E <= 1'b1;
#10 in_E <= 1'b0;
#10 in_x <= ~in_x;
#10 in_x <= ~in_x; in_E <= 1'b1;
#10 in_E <= 1'b0;
#10 in_x <= ~in_x;
#10 in_x <= ~in_x; in_E <= 1'b1;
#10 in_E <= 1'b0;
#10 in_x <= ~in_x;
#10 in_x <= ~in_x; in_E <= 1'b1;
$finish;
end
endmodule