Host command: /opt/cadence/LDV/tools/verilog/bin/verilog.exe
Command arguments:
    sep_tb.v
    sep.v
    alu_slice.v
    mux_4to1.v
    mux_8to1_16bit.v
    mux_2to1_16bit.v
    adder_1bit.v
    reg_16bit.v
    reg_12bit.v
    reg_12bit_pc.v
    reg_12bit_sp.v
    reg_8bit.v
    reg_4bit.v
    memory_unit.v
    sep_alu.v
    RAM_4096x16.v
    reg_32bit.v

Tool:	VERILOG-XL	04.10.010-s log file created Dec  8, 2005  18:40:18
Tool:	VERILOG-XL	04.10.010-s   Dec  8, 2005  18:40:18

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Compiling source file "sep_tb.v"
Compiling source file "sep.v"
Compiling source file "alu_slice.v"
Compiling source file "mux_4to1.v"
Compiling source file "mux_8to1_16bit.v"
Compiling source file "mux_2to1_16bit.v"
Compiling source file "adder_1bit.v"
Compiling source file "reg_16bit.v"
Compiling source file "reg_12bit.v"
Compiling source file "reg_12bit_pc.v"
Compiling source file "reg_12bit_sp.v"
Compiling source file "reg_8bit.v"
Compiling source file "reg_4bit.v"
Compiling source file "memory_unit.v"
Compiling source file "sep_alu.v"
Compiling source file "RAM_4096x16.v"
Compiling source file "reg_32bit.v"

Warning!  Port sizes differ in port connection (port 2)     [Verilog-PCDPC]    
          "sep.v", 552: SP_out

Warning!  Port sizes differ in port connection (port 3)     [Verilog-PCDPC]    
          "sep.v", 552: AR_out

Warning!  Port sizes differ in port connection (port 4)     [Verilog-PCDPC]    
          "sep.v", 552: PC_out
Highest level modules:
sep_tb
a4to16_decoder
reg_8bit
reg_32bit

L37 "sep_tb.v": $finish at simulation time 3004000
3 warnings
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.6 secs to compile + 0.2 secs to link + 3.2 secs in simulation
End of Tool:	VERILOG-XL	04.10.010-s   Dec  8, 2005  18:40:23