/* mux_2to1_16bit describes a two to one multiplexer that is sixteen bits wide. It should synthesize as purly combinational logic. The single register should optimize out. */ `timescale 1ns/100ps module mux_2to1_16bit(out, sel, in0, in1); input sel; /* mux select line */ input [15:0] in0; /* input 0 */ input [15:0] in1; /* input 1 */ output [15:0] out; /* output of mux */ reg [15:0] out; /* this should optimize out */ /* if any of the inputs to the mux change we want to reevaluate the case statement */ always @(sel or in0 or in1) case (sel) 1'b0 : out <= in0; 1'b1 : out <= in1; /* having a default case ensures that the mux will synthesize as purely combinational logic */ default : out <= in0; endcase endmodule