/**************************************************************************** File: rs_ff_tb.v Author: Jeremy Wood Date: 5-27-04 Desc: This is the testbench description for the Set/Reset Flip Flop ****************************************************************************/ `timescale 1ns/100ps module rs_ff_tb; reg set; // set line reg reset; // reset line reg clock; // clock line wire Q; // Q output of the flip flop integer fid; // file handle for output file // Create an instance of the flip flop for testing rs_ff flipflop (Q, set, reset, clock); // Setup the clock signal to be used initial begin clock = 1'b0; forever #10 clock <= ~clock; end // Simulate the flip flop initial begin // Setup the logging functions fid = $fopen ("./rs_ff.out"); $fmonitor (fid, $time, " set = %b, reset = %b, Q = %b", set, reset, Q); // Setup dump file and parameters $dumpfile ("./rs_ff.dmp"); $dumpvars (2, rs_ff_tb); // Start the simulation set <= 1'b0; reset <= 1'b0; // First, test that it toggles #12 set <= 1'b1; #12 set <= 1'b0; #12 reset <= 1'b1; #12 reset <= 1'b0; // Second. test error condition #12 set <= 1'b1; reset <= 1'b1; // Third, test recovery from error #12 set <= 1'b0; reset <= 1'b0; #12 set <= 1'b1; // Done #30 $finish; end endmodule